A great number of microcomputers and logic LSIs which include a digital circuit are used in electronic products.
In a digital circuit such as a microcomputer or an LSI, a latch circuit which temporarily holds digital signals for intermediate processed content, or a register circuit (hereinafter, collectively referred to as simply latch circuit) such as a flip-flop which stores one bit of digital information is used on a signal processing path. The latch circuit holds two states, high (H) and low (L) of a digital signal. As the simplest circuit configuration, a circuit configuration (pair inverter) in which two inverter circuits are combined as a pair and mutually cross-connected to each other can be illustrated. In addition, a set-reset flip-flop (SR-FF) circuit in which two NAND circuits or two NOR circuits are combined as a pair and mutually cross-connected to each other, and an edge-triggered D flip-flop (D-FF) circuit in which a plurality of SR-FF circuits are combined, and the logic state of the output is updated in synchronization with clock edges can be also illustrated. Because these circuits are very ordinary known art, their detailed description is omitted. The operation speeds of the circuits are each determined by a turn-on time and a turn-off time of a transistor. Particularly, in an example of a latch circuit using the above-mentioned pair inverter, the operation speed is limited only by the switching speed of a C-MOS (Complementary-MOS) circuit including four MOSFETs (Metal Oxide Semiconductor Field Effect Transistor), and thus circuit operation on the order of nano seconds can be achieved.
However, once the power source to the latch circuits is turned off, the state of each latch circuit is not held but is lost (volatile). In the case of a nonvolatile latch circuit in which the logic states of all latch circuits in a logic circuit are stored regardless of whether the power source is in ON state or OFF state, the logic states immediately before the turning off of the power source can be quickly restored when the power source is turned on again. Thus even when the power source for an electronic device is turned off by a user, the previous states can be fully restored when the power source is turned on again, thereby allowing continuous circuit operation without returning to the initial state.
Although power saving LSIs have been developed along with the progress of finer semiconductor process, steering of leakage current has become difficult because of the progress, and thus the power saving LSIs in use of only finer semiconductor process are approaching the limit. For this reason, an approach to improving power saving is being adopted by elaborately controlling turning ON/OFF of the power source per circuit block within an LSI for unused circuit blocks. However, when the power source for a block is turned off, the logic state of the block is lost, and thus the approach cannot be performed on a circuit block for which continuous processing is needed. To the contrary, in the case where the above-described nonvolatile latch circuit constitutes all of the registers and latch circuits in a logic circuit, a request for the continuous processing can be satisfied.
However, as an example of application to an LSI of a nonvolatile latch circuit in the conventional art, a floating gate memory element (hereinafter referred to as a flash memory) is utilized as a program recording memory of FPGA (Field-Programmable Gate Arrays) or FPLD (Field-Programmable Logic Devices), and thus the application is limited to a memory area formed as a separate area from a logic circuit. This is because erasing or writing information of or to a flash memory needs a time of the order of μs, and thus the duty cycle of the flash memory cannot be synchronized with the duty cycle of the logic circuit. In the case where such a memory is individually installed in each latch circuit in the logic circuit, even when an operation of each latch circuit is completed, recording of information (logic state of the latch circuit) to the memory is not completed, and thus high-speed operation performance of the logic circuit is impaired. Consequently, in order to ensure high-speed operation of the logic circuit, the following processing is necessary: a flash memory is provided separately from the logic circuit; before the power source is turned off, the state in the logic circuit is transferred to the flash memory; and when the transfer is completed the power source is turned off. However, there is a problem in that in the case of a sudden power off, all the latch states in the logic circuit cannot be transferred to the flash memory in time, and thus the recording cannot be completed. The voltage required for writing or erasing of a flash memory is generally substantially higher than the power source voltage of a logic circuit. Therefore, a write operation to the flash memory cannot be directly performed based on an output signal of the logic circuit. Consequently, the writing or erasing voltage of a flash memory needs to be supplied from the outside of an LSI or be generated inside the LSI chip, and a dedicated driver circuit is necessary.
Furthermore, the manufacturing process of flash memory is complicated in general, and thus forming the logic circuit and the flash memory on the same substrate makes the process even more complicated. In addition, after the transistors that constitute the logic circuit are formed, high-heat process or the like is involved, and therefore the performance of the transistors may be impaired.
In order to cope with these problems, in recent years, the following proposals have been made to configure a nonvolatile latch circuit.
[First Conventional Embodiment]
First, as a first conventional embodiment, a nonvolatile latch circuit using a spin valve memory element as disclosed in PTL 1 is described. The spin valve memory element is also referred to as an MRAM (Magnetic Random Access Memory) cell, which is a memory element using Magneto Resistive Effect in which a resistance value changes in accordance with a magnetization direction. As the Magneto Resistive Effect, Anisotropic Magnetoresistance (AMR), Giant Magnetoresistance (GMR), and Tunnel Magnetoresistance (TMR) are known.
FIG. 19A is a circuit configuration diagram of a nonvolatile latch circuit according to the first conventional embodiment. FIG. 19B is an operation timing chart of the nonvolatile latch circuit according to the first conventional embodiment. A nonvolatile latch circuit 600 illustrated FIG. 19A includes a sense latch circuit 601 and a write current generation circuit 602.
The sense latch circuit 601 includes an inverter circuit 611 which includes a p-type MOSFET 621 and an n-type MOSFET 622, an inverter circuit 612 which includes a p-type MOSFET 623 and an n-type MOSFET 624, p-type MOSFETs 625 and 626, an n-type MOSFET 627, and magnetoresistive elements MTJ0 and MTJ1. The write current generation circuit 602 has n-type MOSFETs 628 to 632.
In FIG. 19A, a data signal is inputted to IN terminal, and an inverted signal of the data inputted to IN terminal is inputted to IN (with an upper bar) terminal. In this state, when DATAGET terminal is set from “L” to “H” for a predetermined time period, as illustrated in FIG. 19B, the n-type MOSFET 632 is turned on, and a current i flows to DWL in a direction according to the input data. Accordingly, the resistances of the magnetoresistive elements MTJ0 and MTJ1 change, and one of them changes to a high resistance state and the other changes to a low resistance state. Subsequently, when REFRESHN terminal is set from “H” to “L” for a predetermined time period, the n-type MOSFET 627 is turned OFF, and the p-type MOSFETs 625 and 626 are turned ON. Accordingly, a node n1 and a node n2 are temporarily precharged to Vdd. The REFRESHN terminal is then set to “H” again, and the n-type MOSFET 627 is turned ON, and thus a current flows to GND via the magnetoresistive elements MTJ0 and MTJ1. The potentials of the node n1 and the node n2 gradually approach the GND potential because of the current. In this process, one of the magnetoresistive elements MTJ0 and MTJ1 that has less resistance value is discharged earlier and the corresponding node potential is reduced earlier. Consequently, the logic of a pair inverter circuit which includes the inverter circuits 611 and 612 converges, and the latch circuit is restored to the logic state according to the resistance relationship between the magnetoresistive elements MTJ0 and MTJ1.
Like this, PLT 1 states the effect that a nonvolatile latch circuit and a flip-flop circuit can be individually disposed in a logic circuit thanks to the nonvolatile latch circuit 600 using a magnetoresistive element, and the operation speed of the entire logic circuit is not impaired because high-speed rewrite to the magnetoresistive element is possible. PLT 1 also discloses that a high voltage which is different from the voltage necessary for a logic operation in rewriting to a memory element is unnecessary.
[Second Conventional Embodiment]
Next, as a second conventional embodiment, a nonvolatile latch circuit using a ReRAM (Resistive RAM) cell as disclosed in PLT1 is described. The ReRAM cell is a variable resistance element whose resistance value changes by application of an electrical stress (mainly electrical pulse). PLT 1 discloses an element in which a resistance film comprising ZnCdS is interposed between a silver (Ag) electrode and a platinum (Pt) electrode. The variable resistance element in this conventional embodiment changes to a high resistance state under application of a voltage which causes a current to flow from BE (Pt) electrode to TE (Ag) electrode, and exceeds a predetermined voltage level, or changes to a low resistance state under application of a voltage which causes a current to flow from TE (Ag) electrode to BE (Pt) electrode, and exceeds a predetermined voltage level. A nonvolatile latch circuit is configured by connecting the element as illustrated in FIG. 20.
FIG. 20 is a circuit configuration diagram of a nonvolatile latch circuit according to a second conventional embodiment. A nonvolatile latch circuit 700 illustrated in FIG. 20 includes variable resistance elements 711 and 712. The variable resistance element 711 and the variable resistance element 712 must be reset in a high resistance state. In a latch operation at normal operation time, Vctrl is pulled up to Vdd, and the variable resistance elements 711 and 712 are already in a high resistance state regardless of whether BL and BL_B is at the GND level or the Vdd level, and thus no resistance change occurs, and a normal latch operation is performed. Next, when the logic state of the latch circuit is stored in the variable resistance element, Vctrl is set to the GND level for a predetermined time period. Accordingly, the variable resistance element between BL and BL_B that is connected to “H” side changes to a low resistance state. The logic information of the latch circuit which has been stored as a low resistance state is restored in such a manner that when Vctrl is pulled up to Vdd, one of the variable resistance elements which is in a low resistance state is increased in potential earlier than the other variable resistance element, and consequently the side to which the variable resistance element in a low resistance state is connected converges to “H”, and the other side converges to “L.”
In order to return to normal latch operation, it is necessary to reset the variable resistance element in a low resistance state to a high resistance state by increasing the potential of Vctrl terminal higher than Vdd because power consumption increases when a variable resistance element is in a low resistance state.
Thus, according to the example disclosed in PLT 1, a nonvolatile latch circuit can be achieved only by adding two variable resistance elements, and the speed of a normal latch operation is not impaired at all.
[Third Conventional Embodiment]
Next, as a third conventional embodiment, a nonvolatile latch circuit using a ReRAM cell disclosed in PLT 2 and PLT 3 is described.
FIG. 21 is a circuit image diagram illustrating a method of storing the state of a nonvolatile latch circuit according to the third conventional embodiment into a variable resistance element. FIG. 22 is a circuit diagram illustrating a method of restoring the previous latch state based on a resistance state stored in the variable resistance element in the nonvolatile latch circuit according to the third conventional embodiment. In the third preceding embodiment, two variable resistance elements are used as a pair for storing a latch state. A nonvolatile latch circuit 800 illustrated in FIG. 21 is a cross-coupled latch circuit such that an output terminal of an inverter circuit 821 is connected to an input terminal of an inverter circuit 822, and an output terminal of the inverter circuit 822 is connected to an input terminal of the inverter circuit 821. A variable resistance element 811 and a variable resistance element 812 are connected via node x and node y by switching a switch circuit (not shown).
When the nonvolatile latch circuit 800 has a state in which the node x in a High level and the node y is in a Low level, a current flows through the variable resistance elements 811 and 812 in the direction indicated by a voltage application direction A. Then the variable resistance element 811 changes to a state (referred to as HR state, or simply HR) in which a resistance value is high, and the variable resistance element 812 changes to a state (referred to as LR state, or simply LR) in which a resistance value is low.
When the nonvolatile latch circuit 800 has a state in which the node y in a High level and the node x is in a Low level, a current flows through the variable resistance elements 811 and 812 in the direction indicated by a voltage application direction B. Then the variable resistance element 811 changes to LR state and the variable resistance element 812 changes to HR state, and the states of the latch circuits are stored in the respective variable resistance elements.
On the other hand, by switching a switch circuit (not shown), the variable resistance elements 811 and 812 are connected to the power source lines of the inverter circuits 821 and 822 as illustrated in FIG. 22. In this circuit connection, in the case where the variable resistance element 811 is in HR and the variable resistance element 812 is in LR, when the power supply terminal A illustrated in FIG. 22 is pulled up from 0V to the power source voltage VDD, the current flowing through the inverter circuit 821 is reduced, and the current flowing through the inverter circuit 822 is increased. Accordingly, the output of the inverter circuit 821 rises up earlier than the output of the inverter circuit 822, and thus the node y is set to a High level, and the node x approaches a Low level so that the previous latch state is restored. Conversely, in the case where the variable resistance element 811 is in LR and the variable resistance element 812 is in HR, the current flowing through the inverter circuit 821 is increased, and the current flowing through the inverter circuit 822 is reduced. Accordingly, the output of the inverter circuit 822 rises up earlier than the output of the inverter circuit 821, and thus the node x is set to a High level, and the node y approaches a Low level so that the previous latch state is restored.
Thus, according to the configuration of the third conventional embodiment, an effect is obtained that the speed of a normal latch operation is not impaired at all even when a variable resistance element is separated from the latch circuit using a switch circuit. In addition, another effect is obtained that the durability of each variable resistance element can be significantly improved because after a resistance state is read from each variable resistance element, a voltage for causing the previous latch state to be restored is small, and a voltage stress is not applied to the variable resistance element after the restoring.
PTL 4 discloses the characteristic of the cellular structure of a variable resistance element, that is to say, the direction of voltage application and the direction of resistance change are determined as a consequence of configuring the oxide layers included in the variable resistance element in a stacked structure of a first oxide layer having a first oxygen content atomic percentage, and a second oxide layer having an oxygen content atomic percentage which is higher than that of the first oxide layer. PTL 5 discloses that the direction of voltage application and the direction of resistance change are determined as a consequence of utilizing two electrode materials whose standard electrode potentials are respectively high and low, the materials being used for the variable resistance element.
PTL 6 discloses that a load resistance is connected to a variable resistance element in series, and the load characteristic of the load resistance is switched in accordance with whether a change is made to LR state or HR state, where the load resistance for a change to LR state is set to be greater than the load resistance for a change to HR state so that it is necessary in some cases to limit the current for a change to LR state in order to achieve stable resistance change operation of a variable resistance element.
[Citation List]
[Patent Literature]
    [PTL 1] Japanese Unexamined Patent Application Publication No. 2003-157671    [PTL 2] Japanese Unexamined Patent Application Publication No. 2008-85770    [PTL 3] WO 2009/060625    [PTL 4] WO 2008/149484    [PTL 5] WO 2009/050833    [PTL 6] WO 2006/137111[Non Patent Literature]    [NPL 1] “Nonvolatile SRAM Cell”, IEEE 2006, 1-4244-0439-8/06